P-channel FET transistors with a normally-off operation are needed to work in conjunction with N-channel transistors in some integrated circuit (IC) applications.
Most prior art P-channel GaN transistors employ a Schottky junction or PN junction as the gate; however, these transistors have excessive gate leakage current under a negative gate bias.
Li G. et al. in “Polarization-induced GaN on insulator E/D mode p-channel heterostructure FETs,” IEEE Electron Device Letters 2013 describe the use of gate insulator in P-channel GaN transistors. The gate leakage current in the described device is low; however, the p-channel field effect transistor (FET) described has a relatively low on/off current ratio of only about 103.
Shatalov M et al. in “GaN/AlGaN p-channel inverted heterostructure JFET,” IEEE Electron Device Letters 2002 describe another p-channel FET; however, the described device has a normally-on operation rather than a normally-off operation and has a high gate leakage current at a negative gate bias of less than or equal to −2 volts (V) of negative gate bias.
Zimmermann T et al. in “P-channel InGaN HFET structure based on polarization doping,” IEEE Electron Device Letters 2004 describe another p-channel FET; however, the described device also has a normally-on operation and has a high gate leakage current at a negative gate bias of less than or equal to −1V.
Hahn et al. in “P-channel enhancement and depletion mode GaN-based HFETs with quaternary backbarriers,” IEEE Transaction on Electron Devices 2013 describe yet another p-channel device; however, the described device has a high gate leakage current at a negative gate bias of less than or equal to −3V.
What is needed is a p-channel device that has a normally off operation and that has low gate leakage current and a high on/off current ratio. The embodiments of the present disclosure answer these and other needs.